Switching system and method of construction thereof

ABSTRACT

A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.

BACKGROUND OF THE INVENTION

The present invention relates to a switching system for exchangingtime-shared multiplex communication data such as voice and data using afixed-length cell with a routing header, or more in particular to aswitching system suitable for exchanging the burst exchange data and thechannel exchange data such as voice integrally.

A versatile and economical switching system is required which is capableof integrally handling communications not only of the bit rate (64 Kb/s)of typical telephone voice but also of various bit rates from low-speed(several hundred b/s) data to video signal (several Mb/s) and variouscharacteristics (burst and real time characteristics).

A promising method expected to meet this requirement involves switchingall data uniformly using a fixed-length cell with a header containingrouting data. The switching system disclosed in a report entitled "Astudy of an Integrated Line/Packet Message Channel", presented toExchange Division 1832, National General Conference (1988) in memory ofthe 70th anniversary of the foundation of the Electronic InformationCommunications Society is an example. In this example, allcommunications data is transferred by use of a fixed-length block calleda "cell". The switching is derived from a space switch, and in order toprevent a plurality of cells having the same address from colliding witheach other in the space switch, a timed switching function is providedfor each incoming highway. Further, the timed switching functionincludes a switching memory and a waiting buffer memory to realize aline exchange mode requiring a real time characteristic such astelephone voice and a burst exchange mode in which data is sent in burstfashion with some delay which may be allowed. The line exchange modecell is handled preferentially not through a buffer memory forguaranteeing the real time characteristic, while the burst exchange modecell is kept waiting in the buffer memory and is processed when there isany empty time slot.

Another example of the prior art is "TDM Switching System" disclosed inthe JP-A-59-135994. This system, though lacking an express descriptionof the concept of handling two types of characteristics including theline exchange mode and the burst exchange mode, is equipped with afunction to replace the fixed-length cell in terms of time by use of abuffer memory. In the process, the same buffer memory is used forwaiting for a cell and switching thereof. In other words, in order toaccomplish the required waiting, the write address into the cell buffermemory is known from the header. The system comprises waiting matrixmeans to be stored according to the address of the cell.

In the case where a plurality of fixed-length cells are used for theswitching operation, the fact that the cell addresses are not alwaysuniformly distributed may cause the cells destined for the same addressto be concentrated temporarily into an overcrowded condition for thecells to be lost by memory overflow. In the system disclosed in thereport of the present application cited first above, a waiting buffermemory is provided for each highway outgoing to each address to avoidsuch an overcrowded condition. This buffer memory is required to have asufficient capacity to store as many cells as required to preventoverflow, and that it is necessary that such a buffer memory is requiredfor each address separately. The resulting problem of this configurationis the necessity of a great capacity of memory. The second-citedswitching system (JP-A-59-135994), on the other hand, comprises a singlebuffer memory for all incoming highways and a plurality of waitingmatrix means for the cell addresses respectively to store only theaddresses of the buffer memory. This construction is capable ofabsorbing the lack of uniformity among the cells with a comparativelysmall storage capacity. The periodic use of the write addresses of thebuffer memory, however, places the system with the buffer memory inlogically the same state as if fixedly divided for each address. Whenthe waiting time for a given cell of the waiting matrix exceeds apredetermined length, for example, the same write address is used tocause an overwrite of the buffer memory in spite of the fact that therestill remain cells yet to be read. The cell overwritten is erasedundesirably.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a switching systemwhich solves the above-mentioned problem of the prior art by eliminatingthe volume use of a memory and in which cells are not lost by theoverwriting of a buffer memory.

In order to achieve the above-mentioned object, there is providedaccording to the present invention a switching system comprising aplurality of incoming highways (hereinafter referred merely as the"incoming lines") multiplexed in time-sharing fashion, a buffer memory(hereinafter referred to as the "main buffer") into which the arrivingcells are written, means for reading the cells from the main buffermemory in appropriate sequence, separating them in multiplexed way anddistributing them among a plurality of outgoing highways (hereinafterreferred merely as the "outgoing lines") thereby to accomplish theexchange operation, a FIFO (First In First Out) buffer (hereinafterreferred to as the "idle Address FIFO") for storing empty addresses ofthe main buffer memory, means for controlling busy addresses forcorresponding outgoing lines, and an idle address chain for retrieving avacant address from the data output of the idle address FIFO buffer atthe time of writing a cell into the main buffer and returning the readaddress into the data input of the idle address FIFO buffer at the timeof reading a cell from the main buffer.

In writing an arriving cell in the main buffer, an empty address isobtained from an idle address FIFO regardless of the outgoing lineaddressed by the cell. Therefore, as long as the main buffer has anempty address, the cell can be written into any region in the mainbuffer. Even if the addresses of the arriving cells are concentrated ata specified outgoing line, the cells to other addresses should bereduced proportionately, so that the required capacity of the mainbuffer remains unchanged.

Further, until a cell is read out, the address storing the particularcell is not returned to the idle address FIFO, thereby eliminating thedisadvantage which otherwise might result with a cell being overwrittenon the same address erasing another cell stored therein.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 is a functional block diagram showing an embodiment of thepresent invention.

FIGS. 2A to 2C are diagrams for explaining a cell construction used inthe embodiment of FIG. 1.

FIG. 3 is a detailed functional block diagram showing and addresspointer included in FIG. 1.

FIG. 4 is a diagram for explaining the operation of a series-parallelconversion multiplexer included in FIG. 1.

FIG. 5 is a detailed functional block diagram showing an idle addressFIFO included in FIG. 1.

FIG. 6 is a functional block diagram showing another embodiment of thepresent invention.

FIG. 7 is a diagram for explaining the logics of the read access controlin FIG. 6.

FIG. 8 is a functional block diagram showing still another embodiment ofthe present invention.

FIG. 9 is a diagram for explaining a cell construction used in theembodiment of FIG. 8.

FIGS. 10 and 11 are diagrams for explaining a further embodiment of thepresent invention.

FIG. 12 is a functional block diagram showing still another embodimentof the present invention.

FIG. 13 is a detailed functional block diagram showing address FIFOsincluded in FIG. 12.

FIG. 14 is a diagram for explaining still another embodiment of thepresent invention.

FIG. 15 is a functional block diagram showing a space switch included inFIG. 14.

FIG. 16 is a functional block diagram showing still another embodimentof the present invention.

FIG. 17 is a detailed functional block diagram showing address FIFOsincluded in FIG. 16.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention will be explained with referenceto FIG. 1. In FIG. 1, a number n of incoming lines are connected througha series-parallel conversion multiplexer 101 to a data input (DI) of amain buffer 105. The data output (DO) of the main buffer 105 isconnected to a parallel-series conversion multiplex separator and isseparated into a number m of outgoing lines. The output portion of theseries-parallel conversion multiplexer 101 which corresponds to the cellheader is connected to a read address terminal (RA) of a headerconversion table 102. The data output (DO) portion of the headerconversion table 102 which corresponds to a new header, on the otherhand, is connected to the data input of the main buffer 105, the portionthereof corresponding to an empty/busy data (0 for empty) connectedthrough an AND gate 109 to a write enable input (WE) of the main buffer105, and the outgoing number portion thereof connected to a destinationoutgoing number input (DEST) of an address pointer 104. The data input(DI) and the write address (WA) of the header conversion table 102 areconnected to a control system not shown. The data output (DO) of theidle address FFFO 103 is the data input (DI) of the main buffer 105 andconnected to the next write address (NWAD) of the address pointer 104.The empty indication output (EPTY) is connected to the write enableinput (WE) of the main buffer 105 through the AND gate 109. The writeaddress output (WAD) of the address pointer 104 is connected to thewrite address input (WA) of the main buffer 105. The read address output(RAD), on the other hand, is connected through a selector 110 to theread address output (RA) of the main buffer 105 and the data input (DI)of the idle address FIFO 103. The portion of the data output (DO) of themain buffer 105 corresponding to the next read address is connected tothe next read address input (NRAD) of the address pointer 104, and theother portions thereof, that is, those portions corresponding to thecell body, are separated through the parallel-series conversionmultiplex separator 106 into each outgoing line. The output of thecontrol counter 107 is connected to the read counter input (RACNT) ofthe address pointer 104. The empty address register 111 is connected tothe input of the selector 110. The cue state indication output (STS) ofthe address pointer 104 is connected to both the selection input of theselector 110 and the write enable input (WE) of the idle address FIFO103 at the same time.

First, the write operation of the cell into the main buffer will beexplained.

The cells that have arrived from respective incoming lines are subjectedto series-to-parallel conversion at the series-parallel conversionmultiplexer 101 to facilitate the handling of each cell separately. Anexample of the construction of the cell arriving from the incoming linesis shown in FIG. 2A, and the concept of the series-parallel conversionmultiplexing in FIG. 4. The series-parallel conversion multiplexer isgenerally made up of a well-known current called "the barrel shifter".As shown in FIG. 2A, the cell header carries a logic channel numberwritten thereon, whereby the header conversion table 102 is accessed toobtain the data as to whether the cell of a new logic channel number onthe outgoing line side is empty or occupied and a cell destinationoutgoing line number. This data is written in the table with the accessfrom the control system at the time of setting a call. FIG. 2B shows anexample of the output of the header conversion table 102.

The cell destination outgoing line number is applied to the addresspointer 104, and an appropriate write address is obtained accordingly.The write address is applied in advance from the idle address FIFO 103.The cell is written into the main buffer 105 by use of this same writeaddress. If the cell is empty or the idle address FIFO is empty (thatis, the main buffer has no empty address), the output of the AND gate109 is "L", and therefore no data is written in the main buffer 105. Atthe same time, the read clock (RCK) of the idle address FIFO is also "L"so that the no output of the empty address is produced.

Now, the read operation will be explained. The cell is read inaccordance with the number generated by the control counter 107, and aread address is obtained from the address pointer 104 and is used as aread address of the main buffer. The value of the control counter 107corresponds to the outgoing line number. Specifically, cells are readone by one sequentially for each outgoing line. The address used as aread address is applied to the data input (DI) of the idle address FIFO103 and is used again as a write address. If there is no cell addressedto a given outgoing line in the main buffer, a cue state indicationoutput (STS) is produced, so that an address stored in the empty celladdress register 111 is selected as a read address of the main buffer105 by the selector 110. The data in the main buffer corresponding tothis address is always kept as an empty cell.

The data output (NWAD) of the idle address FIFO is stored in the mainbuffer together with the cell as next address information. This is toindicate the storage address of the next cell at the same destination asthe cell destination outgoing line. A detailed operation will beexplained below with reference to FIG. 3. The cell construction in themain buffer is shown in FIG. 2C.

Now, the configuration and operation of the address pointer 104 will beexplained with reference to FIG. 3. The outgoing number input (DEST) isconnected to the input of the outgoing line number decoder 301 and theselection input of the address selector 308. A number m of decodeoutputs of the outgoing number decoder 301 are connected respectively tothe clock inputs of a number m of write registers (WR_(l) to m) 302 to303. The next write address (NWAD) applied from an external idle addressFIFO is connected to the input of each write register, and the output ofeach write register is produced as a write address output (WAD) throughthe write address selector 308. The control counter input (RACNT), onthe other hand, is connected to the decoder 311 and the selection inputof the read address selector 309. A number m of decode outputs of thedecoder 311 are connected as clock inputs of a number m of readregisters (RR₁ to m) 304 to 305, respectively through a gate. The nextread address input (NRAD) from an external source is connected to theinput of each read register, the output of which makes up a read address(RAD) through the read address selector 309. Non-coincidence detectors306 to 307 are supplied with outputs of a corresponding write register,and read register respectively, the outputs of which make up a cue stateindication output (STS) through a non-coincidence data selector 310. Theoutputs of the non-coincidence detectors, on the other hand, are alsoconnected to one of the inputs of the gate.

The portions of a number m of outputs of the write registerscorresponding to the outgoing lines thereof are selected by the writeaddress selector 308 in response to the outgoing line number input(DEST) thereby to make up an address output (WAD). In the process, acorresponding value held in the write register by the decode output ofthe outgoing line number decoder 301 is updated to the value (NWAD)supplied from the idle address FIFO. As a result, the NWAD valueimmediately before being updated corresponds to the write address forthe next-arriving cell of the same address as the destination outgoingline number of the cell to be just written. If this NWAD value is storedin the main buffer together with the cell about to be just written,therefore, it is possible to know, when this cell is read out, fromwhich address the next cell destined to the same outgoing line is to beread. In reading a cell, a read register output is selected by a readaddress selector with the value of the control counter 107 as aselection input, and the value held in the register is produced as aread address output (RAD). This output is thus used as a read addressoutput. At the same time, the value held in the read register selectedis updated by the output of the decoder 311. The input of the readregister involved is the next read address stored together with the cellat the time of the write operation which is read out of the main buffer,and therefore the address of the next cell destined to the same outgoingline can be held in the read register.

FIG. 5 shows a configuration of the idle address FIFO 103. The idleaddress FIFO 103 includes a memory 501, a write counter (WCNT) 502, aread counter (RCNT) 503 and a coincidence detector 504. The writecounter 502 is a ring counter for producing a write address (WA) andcounting the same number as the addresses of the memory 501. The readcounter 503 is for producing a read address (RA) and makes up a ringcounter for counting the same number as the addresses of the memory 501.When the values of these two counters coincide with each other, itindicates the memory is empty. This condition is detected by thecoincidence detector 504 to produce an empty output (EPTY). In this way,this circuit has the same function as a FIFO as a whole.

Now, another embodiment of the invention will be explained withreference to FIG. 6. The switching system shown in FIG. 6 operatesbasically on the same principle as the one shown in FIG. 1. In addition,however, the system in FIG. 6 has a preferential control mechanism. InFIG. 6, the component parts identical to those in FIG. 1 are denoted bythe same reference numerals as in FIG. 1 respectively and will not bedescribed again. The embodiment of FIG. 6 is different from that of FIG.1 most conspicuously in that the embodiment of FIG. 6 has a plurality ofaddress pointers. It is assumed that there are three preferentialclasses called class 1(C1), class 2(C2) and class 3(C3).

The output of the header conversion table 102 in FIG. 6 includes a classindication. The class indication output is connected to the input of theclass decoder (CDEC) 605 and the selection input of the write classselector (WSEL) 606. Each decoder output of the class decoder (CDEC) 605is connected to the write address enable input (WAEN) of the addresspointer of each corresponding class. Of the decoder outputs of the classdecoder (CDEC) 605, the output C2 is changed into C2' through an ANDgate supplied with the output of the up-down counter 608. The outputsC1, C3 of the class decoder (CDEC) 605 and the OR output of C2' areconnected to the write enable (WE) of the main buffer 105. Each cuestate indication output (STS) of the address points corresponding toeach class including the address pointer (class 1) 601, address pointer(class 2) 602, and the address pointer (class 3) 603 is connected to theinput of the read access control 604. The relationship between the inputand output of the read access control is shown, for example, in FIG. 7.The output of the read access control 604 is connected to the input ofthe read class selector (RSEL) 607 and the decoder (REDEC) 609. Thedecode output of the decoder (REDEC) 609 is connected to the readaddress enable input (RAEN) of the address pointer of a correspondingclass on the one hand and a logical sum of the decode outputs isconnected to the write enable input (WE) of the idle address FIFO on theother hand. The up-down counter 608 is supplied with the read addressenable input (RAEN) of class 2 as an up input and C2' as a down input.The classes are so defined that class 1 is small in delay tim with a lowcell loss rate, class small in delay time with somewhat large cell lossrate, and class 3 somewhat long in delay time with small cell loss rate.Class 2, in spite of a somewhat larger cell loss rate, is superior toother classes, and therefore limits the usable capacity of a mainbuffer. Specifically, the capacity usable for the up-down counter 608 isset by conversion in the number of cells. The up-down counter 608 isdecremented by write and incremented by read when this counter becomeszero, therefore, it indicates that the main buffer is used to the limit.Under this condition, the output C2' becomes "L" and no new write occursfor this class. As a result, the class 2 cell that has arrived isdiscarded. On the other hand, the read priority order is set by the readaccess control in such a manner that the class 1 has the least delaytime and the class 3 the largest. Specifically, the operation isperformed for each outgoing line in such a way that if the class 1 cellis in the main buffer, it is read in the first place, and when the class1 cue disappears, the class 2 cell is read out. With the disappearanceof the class 2 cue, the class 3 cell is read out.

With the arrival of a cell, the class to which the particular cellbelongs is identifiable by the output of the header conversion table102, so that the write address enable output (WAEN) is applied to theaddress pointer corresponding to the particular class by the classdecoder 605. The write address output (WAD) produced from the addresspointer, on the other hand, is selected by the write class selector(WSEL) 606 and is used as a write address (WA) for the main buffer. Inread operation, by contrast, as mentioned earlier, the read accesscontrol 604 monitors a waiting cue corresponding to each outgoing lineof each class, and effect control to assure that outputs are in theorder of priority among the waiting cues. Specifically, the decodeoutput of the decoder 609 designates an address pointer of the class tobe read, and the read class selector 607 selects a read address outputproduced from the address pointer of the class to be read, thusdetermining the read address of the main buffer.

Now, another embodiment of the present invention will be explained withreference to FIG. 8. The configuration of FIG. 8 is free of the headerconversion table 102 in FIG. 1. In the case under consideration, theconstruction of the cell arriving from the incoming line is shown inFIG. 9. This configuration is suitable for the case in which a headerconversion table is included for each incoming line in the front stageof the switch. This configuration also has an advantage that in amulti-stage construction mentioned later, the header conversion may berendered collectively in advance without respective header conversion byswitches in the respective stages.

In each of the embodiment explained above, the main buffer and the idleaddress FIFO, or the main buffer, idle address FIFO and the addresspointer may be formed in integrated circuits on the same chip. Then, acompact switch and a multi-stage construction described later arerealized.

Now, an embodiment of a switch of a multi-stage construction(multi-stage channel switch) will be explained with reference to FIGS.10 and 11. First, before a specific example, the non-block conditions ofa multi-stage switch will be explained.

A conventional non-block multi-channel switch of Clos type is well knownfor circuit switch. (See Akimaru: "Outline of Current ExchangeEngineering" published by Ohm, 1979, pp. 136 to 137, and C. Clos: AStudy of Non Blocking Networks, Bell System Technical Journal vol. 32,No. 3 (1953)).

A Clos-type multi-stage switch is assumed to have a number m of incominglines of a primary switch, a number r of outgoing lines thereof, anumber k of the incoming and outgoing lines respectively of a secondaryswitch, a number r of incoming lines of the tertiary switch and a numberm of outgoing lines thereof, a number k of the primary switches, anumber r of the secondary switches, and a number k of the tertiaryswitches, so configured that one each of the r outgoing lines of theprimary switch is connected to each of the secondary switches, and oneeach of the k outgoing lines of the secondary switch to each of thetertiary switches. This multi-stage switch construction thus has threestages to satisfy the relationship r≧2m-1 (Clos's formula).

The "non-blocking" is defined to indicate that if both the incoming andoutgoing lines of a switch have an empty capacity, there always exists abus connecting them.

The Clos-type switch is "non-blocking" if it handles a plurality ofcalls of a single speed. In the case where each of the calls has a givenspeed, however, the operating efficiency of the link connecting the unitswitches is reduced, and therefore the switch is not "non-blocking". Ifrespective calls are different in speed, a call of low speed may, forexample, occupy a part of the link capacity, so that in spite of someempty capacity of the link, a high-speed call may not enter there. Dueto this what is called a "decayed phenomenon", the link operatingefficiency is reduced, and therefore a blocking occurs even thoughClos's equation may be satisfied.

This problem is solved by increasing the links of the multi-stage switchspatially, that is, by increasing not only the number of the links butalso the "timing" thereof with an increased link speed. Specifically,although the number of incoming and outgoing lines and links are assumedto be m and r respectively, a switch configuration is such that if thespeed of the incoming and outgoing lines is assumed to be unity, thelink speed is x times higher to satisfy the relationshipr>2{(m-1)/(x-1)}-1.

In this equation, (m-1) on the right side indicates the state in which(m-1) of m incoming lines are busy. (x-1), on the other hand, is thelink speed ratio x, less the unity representing the incoming line speedratio, indicating a limit value of Δ→0 in a state of (x-1+Δ) where agiven link is busy except for a capacity short of a very small amount Δin a single incoming line in terms of speed.

Thus, [(m-1)/(x-1)] indicates the number of links in state that in spiteof a certain empty capacity in the link, a single incoming line cannotbe accomodated, that is, a state where each link is used mostinefficiently. The symbol α indicates a minimum integral number over α.It is thus seen that a number {[(m-1)/(x-1)]-1} of links except for oneare in such a state for both outgoing and incoming lines. Therefore,when the number of links twice as many that is, 2{[(m-1)/(x-1)]-1}, onenew incoming line cannot be accomodated in the links, and if there isanother accomodatable link, that is, if the number is2{[(m-1)/(x-1)-1]}+1, both the incoming line side (primary link) and theoutgoing line side (secondary link) have a link sharing an emptycapacity of at least one channel of incoming line.

Thus, if the number r of the links satisfies the relationsr≧2{[(m-1)/(x-1)]-1}+1, this switch will never block.

An embodiment of the present invention will be explained below withreference to FIG. 10. As shown in FIG. 10, the number n of incoming andoutgoing lines is given as n=mk. A number k of unit switches with anumber m of input terminals and a number (2m-3) of output terminals arearranged as first-stage switches. On the other hand, intermediate-stageswitches include a member (2m-3) unit switches with a number k of inputand output terminals, and final-stage switches a number k of unitswitches with a number (2m-3) input terminals and a number m of outputterminals. As shown in FIG. 10, the respective unit switches areconnected to each other in such a way that the unit switches making upthe first-stage switches are connected to all the unit switches ofintermediate stage, and those making up the intermediate stage to allthe unit switches making up the final stage. In the above-mentionedequation for non-blocking conditions, r≧2{[(m-1)/(x-1)]-1}+1, theembodiment under consideration is associated with a case in which x=2and r=2m-3, satisfying an equality.

The unit switches in each stage may be made up of those explained withreference to FIGS. 6 and 8 or FIGS. 12 and 16.

Now, another embodiment of the multi-stage message channel switch isshown in FIG. 11. Unlike in the embodiment of FIG. 10 in which x=2 andr=2m-3 in the above-mentioned equation for non-blocking conditionsr≧2{[(m-1)/(x-1)]-1}+1, the embodiment under consideration is associatedwith a case in which x=3 and r=m-2. In this case, too, an equality issatisfied. The same approach to the configuration may apply as in FIG.10. The configuration of unit switches is also similar to that of thefirst embodiment in specific points and therefore will not be explainedmore in detail.

According to those embodiments, a multi-stage switch capable ofnon-blocking exchange is realized with the required minimum constructionrequirements.

Now, still another embodiment of unit switches will be explained withreference to FIG. 12. In FIG. 12, the configuration is the same as thatin FIG. 1 except for address FIFOs 1201, the only difference being inconnections. In the embodiment of FIG. 12, the data output (DO) of theidle address FIFO 103 is directly connected to the write address (WA) ofthe main buffer 105. The main buffer 105 is written only with the cellbody, but not with the next address data. The address FIFOs 1201 makingup a point of this configuration will be explained with reference toFIG. 13.

The outgoing line number input (DEST) is connected to the outgoing linenumber decoder (WDEC) 1301, and the m decoder outputs thereof connectedto the write signal inputs (WCK) of a number m of FIFO buffers 1303 to1304. The data input of the FIFO buffers 1303 to 1304 make up the dataoutput of the idle address FIFO in FIG. 12. The data output of the FIFObuffers 1303 to 1304 make up a read address output (RAD) through theread address selector 1305. The read address selector 1305 uses acontrol counter input (RACNT) as a selection input. The control counterinput (RACNT) is further connected to the input of the read sequencedecoder 1302 and the selection input of the empty state selector (EPSEL)1306. The decode output of the read sequence decoder 1302 is connectedto the read signal (RCK) input of each FIFO buffer. The empty statesignal (EP) of each FIFO buffer makes up a cue state indication output(STS) through empty state selector (EPSEL).

In this embodiment, at the time of writing a cell, an empty address fromthe idle address FIFO is taken out, and used as the write address of themain buffer as it is. At the same time, the same address is written inthe FIFO buffer corresponding to the cell destination outgoing linenumber in the address FIFOs 1201. At the time of reading, on the otherhand, addresses are taken out sequentially from the FIFO buffers, andwith these addresses as read addresses, the cells are read out of themain buffer. When the FIFO buffers are empty, an EP output is produced.

In this configuration, the bufferable number of cells for each outgoingline is limited by the capacity of the FIFO buffers in the addressFIFOs. If this capacity is set to a sufficiently large value, however,this configuration is simple as a whole.

FIG. 14 shows an embodiment of an enlargement of the switch scale. Itcomprises header drive-type time switches 1401 to 1402 and a headerdrive-type space switch 1403. The header drive-type time switches 1401to 1402 correspond to the incoming lines, and each of the outputsthereof is used an input to the header drive-type space switches.

The header drive-type time switch is defined as a switch for replacingthe chronological order of cells in accordance with the header data, andspecifically, may comprise a switching system shown in FIG. 1, 6, 8 or12 (except for the multiplexing and multiplex separator) describedabove. These switching systems depend on the value of the controlcounter for their cell reading. If the control counters of the n headerdrive-type time switches in FIG. 14 are set to always different values(for example, by displacing by one for each), therefore, all the cellsread at the same time have different destination outgoing line numbers.As a result, in the header drive-type space switch 1403, there occurs no"bump" which otherwise might be caused by the fact that the cellssimultaneously applied have the same distination. It is thus possible tomake a simple configuration of the header drive-type space switch asshown in FIG. 15. In FIG. 15, timing circuits 150l to 15n, selectors151l to 151n and selection address generators 152l to 152n are arrangedto correspond to the respective outgoing and incoming lines, and theparts of the incoming and outgoing lines associated with the header datahave all the incoming lines connected to the selection addressgenerator, and the other parts than the incoming line headers thereof tothe selectors corresponding to the respective outgoing lines through thetiming circuits respectively. All the destinations of the cells appliedat the same time are different from each other, and therefore, eachselection address generator is supplied only with one header data with adestination address associated therewith. Upon generation of a selectionaddress corresponding to the incoming line supplied with the particularheader data, the selector performs section associated with thedestination, thus performing the space switching operation in general.

FIG. 16 shows the configuration of FIG. 12 having a preferential controlmechanism added thereto. The data output of the header conversion table102 has a class indication output, which is connected to the class input(CLS) of the address FIFOs 1601.

FIG. 17 is a diagram showing a configuration of the address FIFOs withthe preferential control function. The component parts included in thisdiagram which are similar to those in FIG. 13 are not explained.According to the embodiment under consideration, there are two clases ofreading order, preferential and non-preferential. Thus, there are twoFIFO buffers (such as 1702 and 1704) for each outgoing line. The writesignal input (WCK) of the FIFO buffer is the logical porduct of thedecoder output of the outgoing line number decoder 1301 and that of theclass data decoder 1701. The read signal input (RCK), on the other hand,is the logical product of the decode output of the read sequence decoder1302 and the empty state indication output (EP) of each FIFO. Accordingto this configuration at the time of writing a cell, the write address(WAD) is stored in a FIFO buffer associated with the outgoing linenumber and class thereof, while at the time of reading a cell, the readaddress is always produced from the FIFO on this side until the FIFO onpreferential read side (such as 1702) becomes empty. And only after thisFIFO becomes empty, the other FIFO (such as 1704) is read.

This embodiment has two classes of order of priority relating to thedelay time. Instead, the FIFO buffers may be increased for each class tomeet a multiplicity of classes. Also, the requirement for classificationaccording to loss rate may be satisfied by controlling the capacity ofthe FIFO buffers.

It will thus be understood that according to the present invention thereoccurs no loss of a cell which otherwise might be caused when a new cellis read before a cell is read out of the main buffer. Also, all theareas of the main buffer may be used for all outgoing lines in common,and therefore the memory capacity is usable with high efficiency even ifcell distinations are concentrated on a specific outgoing line. As aresult, cells are not hardly discarded. This fact is especiallyadvantageous in communications of strong burst characteristic in whichcells of the same destinations arrive at a given moment.

We claim:
 1. A switching system comprising a plurality of fixed-lengthcells each including a header section and a data section for exchangingcommunication message between a plurality of incoming highways and aplurality of outgoing highways on the basis of the data contained in theheader section, in which a plurality of incoming highways aremultiplexed in time division, the cells that arrive are written in amain buffer, and the cells thus written are read out in an appropriateorder, separated in multiplex ways and distributed among a plurality ofoutgoing highways thereby to perform the switching and bufferingoperations, said switching system further comprising an idle addressFIFO (First in First Out) buffer for storing an empty address of themain buffer and means for controlling the write and read operation ofthe main buffer, the empty idle address being retrieved out of the dataoutput of the idle address FIFO buffer at the time of writing the cellinto the main buffer, the read address being returned to the data inputof the idle address FIFO buffer at the time of reading the cell from themain buffer, wherein the control means includes write registers andreads registers in the same number as the outgoing highwayscorresponding to the respective incoming highways, the data output ofthe idle address FIFO buffer is connected to the input terminals of thewrite registers and the data input terminal of the main bufferrespectively, the output terminals of the plurality of write registersare connected to the write address terminal of the main buffer through aselector with a selection input as the destination outgoing highwaynumber of arriving cell, the same address of the main buffer beingwritten with an arriving cell of an address and the next-arriving cellof the same destination as the first cell of the next address as a setat the time of writing a cell into the main buffer, said next addressbeing used to update the write register corresponding to the outgoinghighway making up the destination of the particular cell, the dataoutput terminals of the main buffer being connected to the inputterminals of the respective read registers, the output terminals of theplurality of read registers being connected to the read address terminalof the main buffer through a selector with a selection input as thecounter output for generating a read timing for each outgoing highway onthe one hand and to the data input of the idle address FIFO on theother, the set of the cell and the next address being read and the readregister associated with the highway being updated by the next addressat the time of reading the cell from the main buffer, thereby switchingthe cells and buffering in chain for each destination outgoing highway.2. A switching system according to claim 1, wherein arriving cells bearclasses for identifying the handling conditions, different classesrepresenting different delay times due to the cell buffering guaranteedby the switch, the switching system further comprising a plurality ofsets each including a write register and a read register, said sets(referred to as "the address pointers") being in the same number as theclasses, said write and read registers being in the same numbers as thehighways, means selecting an address pointer to be used for the classassigned to a particular cell when the cell is written in the mainbuffer, means for producing a read address by selecting an addresspointer of the class most severe against the delay time when the cell isread out, and means detecting the presence or absence of a waiting cuefor a cell associated with a given outgoing highway of the same classand selecting the next most severe class of the address pointer in theabsence of a waiting cue.
 3. A circuit component part for a switchingsystem according to claim 1, wherein the main buffer and the idleaddress FIFO are mounted in the same chip.
 4. A circuit component partfor a switching system according to claim 1, wherein the main buffer,the idle address FIFO and the control means are mounted in the samechip.
 5. A switching system comprising a plurality of fixed-length cellseach including a header section and a data section for exchangingcommunication message between a plurality of incoming highways and aplurality of outgoing highways on the basis of the data contained in theheader section, in which a plurality of incoming highways aremultiplexed in time division, the cells that arrive are written in amain buffer, and the cells thus written are read out in an appropriateorder, separated in multiplex ways and distributed among a plurality ofoutgoing highways thereby to perform the switching and bufferingoperations, said switching system further comprising an idle addressFIFO (First In First Out) buffer for storing an empty address of themain buffer and means for controlling the write and read operation ofthe main buffer, the empty idle address being retrieved out of the dataoutput of the idle address FIFO buffer at the time of writing the cellinto the main buffer, the read address being returned to the data inputof the idle address FIFO buffer at the time of reading the cell from themain buffer, wherein each arriving cell bears a class for identifyingthe handling conditions, different classes representing different celldiscarding rates guaranteed by the switch, the switching system furthercomprising an up-down counter for counting down when a specified classof cell is written in the main buffer, said counter being counted upwhen said cell is read out, the cells of the same class being prohibitedfrom being written into the main buffer and the cell discarded upondetection that the count of the up-down counter becomes zero.
 6. Aswitching system comprising a plurality of fixed-length cells eachincluding a header section and a data section for exchangingcommunication message between a plurality of incoming highways and aplurality of outgoing highways on the basis of the data contained in theheader section, in which a plurality of incoming highways aremultiplexed in time division, the cells that arrive are written in amain buffer, and the cells thus written are read out in an appropriateorder, separated in multiplex ways and distributed among a plurality ofoutgoing highways thereby to perform the switching and bufferingoperations, said switching system further comprising an idle addressFIFO (First In First Out) buffer for storing an empty address of themain buffer and means for controlling the write and read operation ofthe main buffer, the empty idle address being retrieved out of the dataoutput of the idle address FIFO buffer at the time of writing the cellinto the main buffer, the read address being returned to the data inputof the idle address FIFO buffer at the time of reading the cell from themain buffer, comprising FIFO buffers (referred to as "the addressFIFOs") in the same number as the highways, in which the data output ofthe idle address FIFO buffer for storing an empty address of the mainbuffer is connected to the input terminals of a plurality of the addressFIFOs and the write address input of the main buffer, the outputterminals of the address FIFOs being connected to the data input of theidle address FIFO buffer and the read address terminal of the mainbuffer through a selector with a control counter output as a selectionoutput.
 7. A switching system according to claim 6, wherein each of thearriving cells has a class for identifying the handle conditions,different classes having different delay times due to the cell bufferingguaranteed by the switch, the switching system comprising a plurality ofaddress FIFOs in the same number as the classes for each outgoinghighway, means for selecting an idle FIFO according to the classassociated with a cells at the time of writing the cell in the mainbuffer, and means for producing a read address by selecting an addressFIFO of a class having more severe conditions against the delay time atthe time of reading the cell from the main buffer.
 8. A switching systemfor exchanging communication data between a plurality of incominghighways and a plurality of outgoing highways by use of a plurality offixed-length cells each having a header section and a data section, thesystem comprising header drive-type time switches corresponding to theincoming highways for replacing the chronological order of the cellsaccording to the header data, and a header drive-type space switch forspatially replacing a cell between highways according to the headerdata, the output of the header drive-type time switch being connected tothe header drive-type space switch, and header drivetype time switchcomprising:means for multiplexing said plurality of incoming highways intime division, means for writing the cells that arrive in a main buffer,and switching means for reading out the cells thus written in anappropriate order, separating said cells in multiplex ways anddistributing said cells among a plurality of outgoing highways therebyto perform switching and buffering operations, said switching meansfurther comprising an idle address FIFO (First In First Out) buffer forstoring an empty address of the main buffer and control means forcontrolling the write and read operation of the main buffer, the emptyidle address being retrieved out of the data output of the idle addressFIFO buffer at the time of writing the cell into the main buffer, theread address being returned to the data input of the idle address FIFObuffer at the time of reading the cell from the main buffer, wherein thecontrol means includes write registers and read registers in the samenumber as the outgoing highways corresponding to the respective incominghighways, the data output of the idle address FIFO buffer is connectedto the input terminals of the write registers and the data inputterminal of the main buffer respectively, the output terminals of theplurality of write registers are connected to the write address terminalof the main buffer through a selector with a selection input as thedesination outgoing highway number of arriving cell, the same address ofthe main buffer being written with an arriving cell of an address andthe next-arriving cell of the same destination as the first cell of thenext address as a set at the time of writing a cell into the mainbuffer, said next address being used to update the write registercorresponding to the outgoing highway making up the destination of theparticular cell, the data output terminals of the main buffer beingconnected to the input terminals of the respective read registers, theoutput terminals of the plurality of read registers being connected tothe read address terminal of the main buffer through a selector with aselection input as the counter output for generating a read timing foreach outgoing highway on the one hand and to the data input of the idleaddress FIFO on the other, the set of the cell and the next addressbeing read and the read register associated with the highway beingupdated by the next address at the time of reading the cell from themain buffer, thereby switching the cells and buffering in chain for eachdestination outgoing highway.
 9. A switching system for exchanging thecommunication data between a plurality of incoming highways and aplurality of outgoing highways by use of a plurality of fixed-lengthcells including a header section and a data section, the systemcomprising header drive-type time switches corresponding to the incominghighways, respectively, for replacing the chronological order of cellsaccording to the header data, and a header drive-type space switch forreplacing the cells spatially between the highways according to theheader data, the output of the header driver-type time switch beingconnected to the input terminals of the header drive-type space switch,said header drive-type time switch comprising:means for multiplexingsaid plurality of incoming highways in time division, means for writingthe cells that arrive in a main buffer, and switching means for readingout the cells thus written in an appropriate order, separating the cellsin multiplex ways and distributing the cells among a plurality ofoutgoing highways thereby to perform the switching and bufferingoperations, said switching means further comprising an idle address FIFO(First In First Out) buffer for storing an empty address of the mainbuffer and control means for controlling the write and read operation ofthe main buffer, the empty idle address being retrieved out of the dataoutput of the idle address FIFO buffer at the time of writing the cellinto the main buffer, the read address being returned to the data inputof the idle address FIFO buffer at the time of reading the cell from themain buffer, comprising FIFO buffers (referred to as "the addressFIFOs") in the same number as the highways, in which the data output ofthe idle address FIFO buffer for storing an empty address of the mainbuffer is connected to the input terminals of a plurality of the addressFIFOs and the write address input of the main buffer, the outputterminals of the address FIFOs being connected to the data input of theidle address FIFO buffer and the read address terminal of the mainbuffer through a selector with a control counter output as a selectionoutput.
 10. In a three-stage link switch comprising a plurality of unitswitches connected in multiple stages for exchanging the communicationdata between a given number of incoming terminals and a given number ofoutgoing terminals, a multi-stage switch comprising a first stageincluding a plurality of unit switches (primary switches) each having anintegral number m of incoming lines, an integral number r of outgoinglines and the ratio of 1 to x between the incoming line speed and theoutgoing line speed, where x is the link speed ratio, a middle stageincluding a plurality of unit switches (secondary switches) each havingan integral number k of incoming lines and an integral number k ofoutgoing lines, and the ratio of 1 to 1 between the incoming line speedand the outgoing line speed, and a final stage including a plurality ofunit switches (tertiary switches) each having an integral number r ofincoming lines, an integral number m of outgoing lines, and the ratio ofx to 1 between the incoming line speed and the outgoing line speed, theprimary switches being in the number of k, the secondary switches in thenumber of r, and the tertiary switches being in the number of k, the routgoing lines of the primary switches being connected to the secondaryswitches respectively, the k outgoing lines of the secondary switchesbeing connected to the tertiary switches respectively, the switch beingconstructed so 1014 as to satisfy the relationshipr≧2{[(m-1)/(x-1)]-1}+1 where the symbol [(m-1)/(x-1)] indicates theminimum integral number equal to or larger than (m-1)/(x-1).
 11. Amulti-stage message chnnale switch according to claim 10, furthercomprising a packet including a header section and a data section, saidcommunication data being exchanged with reference to the data containedin the header section of the packet.
 12. A multi-stage message channelswitch according to claim 10, wherein r=2m-3 and x=2.
 13. A multi-stagemessage channel switch according to claim 10, wherein r=m-2 and x=3. 14.A switching system for handling a plurality of fixed-length cells, eachfixed length cell including a header section and a data section, and forexchanging a communication message contained in the data section of thecell between a plurality of incoming highways and a plurality ofoutgoing highways according to the data contained in the header sectionof the cell, comprising:means for multiplexing said incoming highways intime division; first memory means having addressable storage locationfor storing cells received from said multiplexing means; means fordemultiplexing and distributing data output from said first memory meansamong a plurality of outgoing highways; second memory means for storingan empty address of an empty storage location of the first memory means;and means for controlling the write and read operations of said firstmemory means in accordance with an empty address stored in the secondmemory means.
 15. A switching system according to claim 14, wherein saidcontrolling means includes first means for storing in said first memorymeans an empty address from said second memory means as a next addressalong with a cell received from said multiplexing means, and means forstoring said empty address for use as a write address to store the nextcell received from said multiplexing means for a given outgoing highwayin said first memory means.
 16. A switching system according to claim15, wherein said controlling means further includes second means forstoring a next address read out of said first memory means at the time acell is read out of said first memory means for a given outgoinghighway, and means for reading another cell from said first memory meansfor said given outgoing highway using the address stored in said secondmeans.
 17. A switching system according to claim 16, wherein saidcontrolling means also includes means for storing said address in saidsecond means into said second memory means when that address is used toread said another cell from said first memory means.
 18. A switchingsystem for handling a plurality of fixed-length cells, each fixed-lengthcell including a header section and a data section, and for exchanging acommunication message contained in the data section of the cell betweena plurality of incoming highways and a plurality of outgoing highwaysaccording to the data contained in the header section of the cell,comprising:means for multiplexing said incoming highways in timedivision; a main buffer connected to said multiplexing means and havinga plurality of addressable storage locations for storing cells whicharrive from said multiplexing means; means for demultiplexing anddistributing data output from the main buffer among a plurality ofoutgoing highways; an idle address FIFO buffer for storing an address ofan empty storage location in the main buffer; and means for controllingthe write and read operations of the main buffer in accordance with anaddress stored in said idle address FIFO buffer, including means forstoring the data output of the idle address FIFO buffer in the mainbuffer .[.at the time of writing the cell into the main buffer.]. at thetime of writing the cell into the main buffer, and for applying a readaddress used in reading a cell from the main buffer to the data input ofthe idle address FIFO buffer for storage therein at the time of readinga cell from the main buffer.
 19. A switching system according to claim18, wherein said main buffer comprises a random access memory.
 20. Aswitching system according to claim 18, wherein said controlling meansincludes means for controlling write addresses for writing cells intosaid main buffer according to a destination outgoing highway of theparticular cell, so that a cell designated to a given outgoing highwaycan be read out of said main buffer selectively. .Iadd.
 21. A switchingsystem for handling a plurality of fixed length cells, each fixed lengthcell including a header section and an information section, to exchangeinformation contained in the information section of cells between aplurality of incoming highways and a plurality of outgoing highwaysaccording to an identifier contained in the header section of the cells,comprising:a serial/parallel converter for converting said incominghighways from serial to parallel; a memory having a plurality ofaddressable storage locations for storing cells received from saidserial/parallel converter; a parallel/serial converter for distributingcells received from said memory to said outgoing highways; a storage forstoring addresses of empty storage locations of said memory; and acontroller for controlling at least one of write and read operations ofsaid memory in accordance with addresses stored in said storage..Iaddend. .Iadd.22. A switching system according to claim 21, whereinsaid controller includes first means for storing in said memory an emptystorage location address from said storage as a next address along witha cell received from said serial/parallel converter, and means forstoring said empty storage location address for use as a write addressto store in said memory the next cell received from said serial/parallelconverter for a given outgoing highway. .Iaddend. .Iadd.23. A switchingsystem according to claim 22, wherein said controller further includessecond means for storing a next address read out of said memory inresponse to a cell being read out of said first memory for a givenoutgoing highway, and means for reading another cell from said memoryfor said given outgoing highway using an address stored in said secondmeans. .Iaddend. .Iadd.24. A switching system according to claim 23,wherein said controller also includes third means for storing saidaddress stored in said second means also into said storage in responseto that address being used to read said another cell from said memory..Iaddend. .Iadd.25. A switching system for handling a plurality of fixedlength cells, each fixed length cell including a header section and aninformation section, to exchange information contained in theinformation section of cells between a plurality of incoming highwaysand a plurality of outgoing highways according to an identifiercontained in the header section of the cells, comprising:aserial/parallel converter for converting said incoming highways fromserial to parallel; a buffer connected to receive cells from saidserial/parallel converter and having a plurality of addressable storagelocations for storing said cells; a parallel/serial converter fordistributing cells received from said buffer to said outgoing highways;an idle address FIFO storage for storing addresses of empty storagelocations in said buffer; a controller for controlling at least one ofwrite and read operations of the buffer in accordance with addressesstored in said idle address FIFO storage, including means for storing anaddress from the idle address FIFO storage into the buffer inconjunction with the writing of a cell into the buffer and for applyinga read address used in reading a cell from the buffer to said idleaddress FIFO storage so as to be stored therein. .Iaddend. .Iadd.26. Aswitching system according to claim 25, wherein said buffer comprises arandom access memory. .Iaddend. .Iadd.27. A switching system accordingto claim 25, wherein said controller includes means for controllingwrite addresses for writing cells into said buffer according to adestination outgoing highway of the particular cell. .Iaddend. .Iadd.28.A switching method for handling a plurality of fixed length cells, eachfixed length cell including a header section and an information section,to exchange information contained in the information section of cellsbetween a plurality of incoming highways and a plurality of outgoinghighways according to an identifier contained in the header section ofthe cells, comprising:(a) supplying cells in sequence to an addressablebuffer memory for storage in respective storage locations of said buffermemory according to respective write addresses; (b) reading cells from arespective storage locations of said buffer memory in accordance withrespective read addresses; (c) storing in a storage addresses of emptystorage locations of said buffer memory; and (d) determining one of saidwrite addresses and said read addresses in accordance with addressesstored in said storage. .Iaddend. .Iadd.29. A switching system forhandling a plurality of fixed-length cells, each fixed length cellincluding a header section and an information section, and forexchanging communication information contained in the informationsection of a cell between a plurality of incoming highways and aplurality of outgoing highways according to data contained in the headersection of the cell, comprising:means for multiplexing cells in saidincoming highways in time division; first memory means for storing cellsreceived from said multiplexing means; means for demultiplexing dataoutput from said first memory means among a plurality of outgoinghighways; second memory means for storing an address of an empty storagelocation of the first memory means; and means for controlling the writeand/or read operations of said first memory means in accordance with anaddress stored in the second memory means. .Iaddend. .Iadd.30. Aswitching system for handling a plurality of fixed-length cells, eachfixed-length cell including a header section and an information section,and for exchanging communication information contained in theinformation section of the cell between a plurality of incoming highwaysand a plurality of outgoing highways according to the data contained inthe header section of the cell, comprising: means for multiplexing saidincoming highways in time division; first memory means connected to saidmultiplexing means for storing cells which arrive from said multiplexingmeans; means for demultiplexing data output from the first memory meansamong a plurality of outgoing highways; second memory means for storingan address of an empty storage location in the first memory means; andmeans for controlling the write and/or read operations of the firstmemory means in accordance with an address stored in said second memorymeans, including means for storing data output from the second memorymeans into the first memory means at the time of writing a cell into thefirst memory means and for applying a read address used in reading acell from the first memory means to the data input to the second memorymeans for storage therein at the time of reading a cell from the firstmemory means. .Iaddend.